The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the LIA logic in the Incremental Track. Chart
Results were generated on 2026-07-25
Benchmarks: 6
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 25393 | 15.95 | 15.95 | 0 | 6 | 0 | 0 | 0 |
| SMTInterpol | 0 | 25393 | 25.76 | 25.76 | 0 | 6 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 15044 | 68.31 | 68.31 | 0 | 6 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 0.04 | 0.05 | 0 | 6 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 6 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 25393 | 15.95 | 15.95 | 0 | 6 | 0 | 0 | 0 |
| SMTInterpol | 0 | 25393 | 25.76 | 25.76 | 0 | 6 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 15044 | 68.31 | 68.31 | 0 | 6 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 0.04 | 0.05 | 0 | 6 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 6 | 0 | 0 | 0 |