The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the BVFPLRA logic in the Incremental Track. Chart
Results were generated on 2026-07-25
Benchmarks: 9
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| Bitwuzla | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Bitwuzla | 0 | 4782 | 694.29 | 694.29 | 0 | 9 | 0 | 2 | 0 |
| Bitwuzla-fixed n | 0 | 4782 | 695.99 | 695.99 | 0 | 9 | 0 | 2 | 0 |
| cvc5 | 0 | 2964 | 23.13 | 23.13 | 0 | 9 | 0 | 6 | 0 |
| UltimateEliminator+MathSAT | 0 | 2157 | 83.84 | 83.84 | 0 | 9 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 0.05 | 0.07 | 0 | 9 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 9 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 2964 | 23.13 | 23.13 | 0 | 9 | 0 | 6 | 0 |
| Bitwuzla-fixed n | 0 | 1565 | 44.83 | 44.83 | 0 | 7 | 2 | 1 | 0 |
| Bitwuzla | 0 | 1565 | 45.19 | 45.19 | 0 | 7 | 2 | 1 | 0 |
| UltimateEliminator+MathSAT | 0 | 721 | 59.73 | 59.73 | 0 | 8 | 1 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 0.05 | 0.07 | 0 | 9 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 9 | 0 | 0 | 0 |