SMT-COMP 2026

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2026

BV (Incremental Track)

Competition results for the BV logic in the Incremental Track. Chart

Results were generated on 2026-07-25

Benchmarks: 18
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Parallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
cvc5--cvc5

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedUnsolvedAbstainedTimeoutMemout
Bitwuzla-fixed n038856525.47525.47018000
cvc50358312391.912391.91018070
SMTInterpol0245352388.082388.08018060
UltimateEliminator+MathSAT018912178.40178.40018010
z3-BooledASS ne00
(base +0)		0.110.14018000
Bitwuzla138379458.43458.43018000
z3-BooledASS-base n000.000.00018000
(base +/- n): for derived solvers: increment over base solver
ne: not eligible for winning as it does not substantially improve over the base solver (at least 10 % improvement in PAR2 score) n: non-competing solver

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedUnsolvedAbstainedTimeoutMemout
cvc502512594.9094.90010840
Bitwuzla-fixed n022365126.51126.51010800
SMTInterpol017997100.13100.13014420
UltimateEliminator+MathSAT01377099.9899.98016200
z3-BooledASS ne00
(base +0)		0.110.14018000
Bitwuzla121888111.14111.14010800
z3-BooledASS-base n000.000.00018000
(base +/- n): for derived solvers: increment over base solver
ne: not eligible for winning as it does not substantially improve over the base solver (at least 10 % improvement in PAR2 score) n: non-competing solver