The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the AUFDTNIRA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 545
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | z3-BooledASS | z3-BooledASS |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 438 (base +1) | 92.05 | 146.04 | 438 | 0 | 438 | 107 | 0 | 103 | 0 |
| cvc5 | 0 | 438 | 675.44 | 730.13 | 438 | 0 | 438 | 107 | 0 | 49 | 0 |
| cvc5-cvc5-xyz ne | 0 | 438 (base +0) | 681.17 | 735.20 | 438 | 0 | 438 | 107 | 0 | 49 | 0 |
| SMTInterpol | 0 | 342 | 1176.02 | 594.64 | 342 | 0 | 342 | 203 | 0 | 203 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 438 | 700.30 | 754.35 | 438 | 0 | 438 | 107 | 0 | 49 | 0 |
| z3-BooledASS-base n | 0 | 437 | 87.69 | 141.11 | 437 | 0 | 437 | 108 | 0 | 103 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 438 (base +1) | 92.05 | 146.04 | 438 | 0 | 438 | 107 | 0 | 103 | 0 |
| cvc5 | 0 | 438 | 675.44 | 730.13 | 438 | 0 | 438 | 107 | 0 | 49 | 0 |
| cvc5-cvc5-xyz ne | 0 | 438 (base +0) | 681.17 | 735.20 | 438 | 0 | 438 | 107 | 0 | 49 | 0 |
| SMTInterpol | 0 | 342 | 1176.02 | 594.64 | 342 | 0 | 342 | 203 | 0 | 203 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 438 | 700.30 | 754.35 | 438 | 0 | 438 | 107 | 0 | 49 | 0 |
| z3-BooledASS-base n | 0 | 437 | 87.69 | 141.11 | 437 | 0 | 437 | 108 | 0 | 103 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS | 0 | 438 (base +1) | 92.05 | 146.04 | 438 | 0 | 438 | 1 | 106 | 1 | 0 |
| cvc5 | 0 | 438 | 675.44 | 730.13 | 438 | 0 | 438 | 1 | 106 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 438 (base +0) | 681.17 | 735.20 | 438 | 0 | 438 | 1 | 106 | 0 | 0 |
| SMTInterpol | 0 | 342 | 1176.02 | 594.64 | 342 | 0 | 342 | 97 | 106 | 97 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 438 | 700.30 | 754.35 | 438 | 0 | 438 | 1 | 106 | 0 | 0 |
| z3-BooledASS-base n | 0 | 437 | 87.69 | 141.11 | 437 | 0 | 437 | 2 | 106 | 1 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS | 0 | 438 (base +1) | 92.05 | 146.04 | 438 | 0 | 438 | 3 | 104 | 0 | 0 |
| cvc5 | 0 | 437 | 94.24 | 148.73 | 437 | 0 | 437 | 57 | 51 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 437 (base +0) | 96.03 | 149.89 | 437 | 0 | 437 | 57 | 51 | 0 | 0 |
| SMTInterpol | 0 | 342 | 1176.02 | 594.64 | 342 | 0 | 342 | 0 | 203 | 0 | 0 |
| z3-BooledASS-base n | 0 | 437 | 87.69 | 141.11 | 437 | 0 | 437 | 5 | 103 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 437 | 96.40 | 150.31 | 437 | 0 | 437 | 57 | 51 | 0 | 0 |