The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the AUFDTLIRA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 1344
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 1194 | 591.00 | 738.52 | 1194 | 0 | 1194 | 150 | 0 | 147 | 0 |
| cvc5-cvc5-xyz ne | 0 | 1193 (base -1) | 610.78 | 758.72 | 1193 | 0 | 1193 | 151 | 0 | 148 | 0 |
| z3-BooledASS ne | 0 | 1189 (base +2) | 408.22 | 554.13 | 1189 | 0 | 1189 | 155 | 0 | 122 | 0 |
| SMTInterpol | 0 | 1004 | 10496.38 | 6893.93 | 1005 | 0 | 1005 | 339 | 0 | 282 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 1194 | 597.76 | 745.81 | 1194 | 0 | 1194 | 150 | 0 | 147 | 0 |
| z3-BooledASS-base n | 0 | 1187 | 276.33 | 421.83 | 1187 | 0 | 1187 | 157 | 0 | 125 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 1194 | 591.00 | 738.52 | 1194 | 0 | 1194 | 150 | 0 | 147 | 0 |
| cvc5-cvc5-xyz ne | 0 | 1193 (base -1) | 610.78 | 758.72 | 1193 | 0 | 1193 | 151 | 0 | 148 | 0 |
| z3-BooledASS ne | 0 | 1189 (base +2) | 408.22 | 554.13 | 1189 | 0 | 1189 | 155 | 0 | 122 | 0 |
| SMTInterpol | 0 | 1005 | 11701.09 | 7478.47 | 1005 | 0 | 1005 | 339 | 0 | 282 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 1194 | 597.76 | 745.81 | 1194 | 0 | 1194 | 150 | 0 | 147 | 0 |
| z3-BooledASS-base n | 0 | 1187 | 276.33 | 421.83 | 1187 | 0 | 1187 | 157 | 0 | 125 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 1194 | 591.00 | 738.52 | 1194 | 0 | 1194 | 1 | 149 | 1 | 0 |
| cvc5-cvc5-xyz ne | 0 | 1193 (base -1) | 610.78 | 758.72 | 1193 | 0 | 1193 | 2 | 149 | 2 | 0 |
| z3-BooledASS | 0 | 1189 (base +2) | 408.22 | 554.13 | 1189 | 0 | 1189 | 6 | 149 | 3 | 0 |
| SMTInterpol | 0 | 1005 | 11701.09 | 7478.47 | 1005 | 0 | 1005 | 190 | 149 | 166 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 1194 | 597.76 | 745.81 | 1194 | 0 | 1194 | 1 | 149 | 1 | 0 |
| z3-BooledASS-base n | 0 | 1187 | 276.33 | 421.83 | 1187 | 0 | 1187 | 8 | 149 | 4 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 1190 | 243.02 | 390.02 | 1190 | 0 | 1190 | 0 | 154 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 1190 (base +0) | 246.60 | 394.13 | 1190 | 0 | 1190 | 0 | 154 | 0 | 0 |
| z3-BooledASS ne | 0 | 1187 (base +1) | 235.83 | 381.46 | 1187 | 0 | 1187 | 31 | 126 | 0 | 0 |
| SMTInterpol | 0 | 980 | 3356.28 | 1615.18 | 980 | 0 | 980 | 38 | 326 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 1190 | 247.83 | 395.34 | 1190 | 0 | 1190 | 0 | 154 | 0 | 0 |
| z3-BooledASS-base n | 0 | 1186 | 237.47 | 382.84 | 1186 | 0 | 1186 | 29 | 129 | 0 | 0 |