The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the AUFDTLIA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 300
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | cvc5 | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 295 | 23090.26 | 23128.30 | 295 | 85 | 210 | 5 | 0 | 5 | 0 |
| cvc5-cvc5-xyz ne | 0 | 295 (base +0) | 23162.09 | 23200.70 | 295 | 85 | 210 | 5 | 0 | 5 | 0 |
| z3-BooledASS ne | 0 | 254 (base +0) | 618.59 | 649.68 | 254 | 40 | 214 | 46 | 0 | 46 | 0 |
| SMTInterpol | 0 | 192 | 1669.45 | 1055.30 | 192 | 1 | 191 | 108 | 0 | 38 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 295 | 23092.48 | 23130.79 | 295 | 85 | 210 | 5 | 0 | 5 | 0 |
| z3-BooledASS-base n | 0 | 254 | 621.99 | 653.15 | 254 | 40 | 214 | 46 | 0 | 46 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 295 | 23090.26 | 23128.30 | 295 | 85 | 210 | 5 | 0 | 5 | 0 |
| cvc5-cvc5-xyz ne | 0 | 295 (base +0) | 23162.09 | 23200.70 | 295 | 85 | 210 | 5 | 0 | 5 | 0 |
| z3-BooledASS ne | 0 | 254 (base +0) | 618.59 | 649.68 | 254 | 40 | 214 | 46 | 0 | 46 | 0 |
| SMTInterpol | 0 | 192 | 1669.45 | 1055.30 | 192 | 1 | 191 | 108 | 0 | 38 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 295 | 23092.48 | 23130.79 | 295 | 85 | 210 | 5 | 0 | 5 | 0 |
| z3-BooledASS-base n | 0 | 254 | 621.99 | 653.15 | 254 | 40 | 214 | 46 | 0 | 46 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 85 | 23011.06 | 23023.10 | 85 | 85 | 0 | 0 | 215 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 85 (base +0) | 23081.37 | 23093.83 | 85 | 85 | 0 | 0 | 215 | 0 | 0 |
| z3-BooledASS ne | 0 | 40 (base +0) | 6.76 | 11.63 | 40 | 40 | 0 | 45 | 215 | 45 | 0 |
| SMTInterpol | 0 | 1 | 0.63 | 0.54 | 1 | 1 | 0 | 84 | 215 | 32 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 85 | 23012.02 | 23024.27 | 85 | 85 | 0 | 0 | 215 | 0 | 0 |
| z3-BooledASS-base n | 0 | 40 | 6.77 | 11.63 | 40 | 40 | 0 | 45 | 215 | 45 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 214 (base +0) | 611.83 | 638.05 | 214 | 0 | 214 | 1 | 85 | 1 | 0 |
| cvc5 | 0 | 210 | 79.21 | 105.20 | 210 | 0 | 210 | 5 | 85 | 5 | 0 |
| cvc5-cvc5-xyz ne | 0 | 210 (base +0) | 80.71 | 106.87 | 210 | 0 | 210 | 5 | 85 | 5 | 0 |
| SMTInterpol | 0 | 191 | 1668.82 | 1054.77 | 191 | 0 | 191 | 24 | 85 | 6 | 0 |
| z3-BooledASS-base n | 0 | 214 | 615.22 | 641.52 | 214 | 0 | 214 | 1 | 85 | 1 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 210 | 80.45 | 106.51 | 210 | 0 | 210 | 5 | 85 | 5 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 250 | 92.17 | 122.87 | 250 | 40 | 210 | 0 | 50 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 250 (base +0) | 94.45 | 125.37 | 250 | 40 | 210 | 0 | 50 | 0 | 0 |
| z3-BooledASS ne | 0 | 249 (base +0) | 51.05 | 81.47 | 249 | 40 | 209 | 0 | 51 | 0 | 0 |
| SMTInterpol | 0 | 182 | 735.58 | 297.10 | 182 | 1 | 181 | 63 | 55 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 250 | 94.19 | 125.03 | 250 | 40 | 210 | 0 | 50 | 0 | 0 |
| z3-BooledASS-base n | 0 | 249 | 51.66 | 82.17 | 249 | 40 | 209 | 0 | 51 | 0 | 0 |