The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the AUFBVDTNIRA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 904
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz ne | 0 | 532 (base +15) | 10765.96 | 10832.57 | 532 | 0 | 532 | 372 | 0 | 372 | 0 |
| cvc5 | 0 | 517 | 839.23 | 902.95 | 517 | 0 | 517 | 387 | 0 | 359 | 0 |
| SMTInterpol | 0 | 502 | 6597.96 | 4338.44 | 502 | 0 | 502 | 402 | 0 | 388 | 0 |
| z3-BooledASS ne | 0 | 34 (base -475) | 224.49 | 228.65 | 34 | 0 | 34 | 870 | 0 | 398 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 517 | 1060.88 | 1124.60 | 517 | 0 | 517 | 387 | 0 | 359 | 0 |
| z3-BooledASS-base n | 0 | 509 | 192.27 | 254.68 | 509 | 0 | 509 | 395 | 0 | 278 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz ne | 0 | 532 (base +15) | 10765.96 | 10832.57 | 532 | 0 | 532 | 372 | 0 | 372 | 0 |
| cvc5 | 0 | 517 | 839.23 | 902.95 | 517 | 0 | 517 | 387 | 0 | 359 | 0 |
| SMTInterpol | 0 | 502 | 6597.96 | 4338.44 | 502 | 0 | 502 | 402 | 0 | 388 | 0 |
| z3-BooledASS ne | 0 | 34 (base -475) | 224.49 | 228.65 | 34 | 0 | 34 | 870 | 0 | 398 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 517 | 1060.88 | 1124.60 | 517 | 0 | 517 | 387 | 0 | 359 | 0 |
| z3-BooledASS-base n | 0 | 509 | 192.27 | 254.68 | 509 | 0 | 509 | 395 | 0 | 278 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz ne | 0 | 532 (base +15) | 10765.96 | 10832.57 | 532 | 0 | 532 | 340 | 32 | 340 | 0 |
| cvc5 | 0 | 517 | 839.23 | 902.95 | 517 | 0 | 517 | 355 | 32 | 352 | 0 |
| SMTInterpol | 0 | 502 | 6597.96 | 4338.44 | 502 | 0 | 502 | 370 | 32 | 367 | 0 |
| z3-BooledASS ne | 0 | 34 (base -475) | 224.49 | 228.65 | 34 | 0 | 34 | 838 | 32 | 367 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 517 | 1060.88 | 1124.60 | 517 | 0 | 517 | 355 | 32 | 352 | 0 |
| z3-BooledASS-base n | 0 | 509 | 192.27 | 254.68 | 509 | 0 | 509 | 363 | 32 | 246 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 513 | 132.21 | 195.33 | 513 | 0 | 513 | 28 | 363 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 507 (base -6) | 136.57 | 199.16 | 507 | 0 | 507 | 26 | 371 | 26 | 0 |
| SMTInterpol | 0 | 470 | 2822.84 | 1169.97 | 470 | 0 | 470 | 6 | 428 | 0 | 0 |
| z3-BooledASS ne | 0 | 32 (base -476) | 32.22 | 36.12 | 32 | 0 | 32 | 457 | 415 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 513 | 136.82 | 199.92 | 513 | 0 | 513 | 28 | 363 | 0 | 0 |
| z3-BooledASS-base n | 0 | 508 | 165.41 | 227.69 | 508 | 0 | 508 | 107 | 289 | 0 | 0 |