The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the AUFBVDTNIA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 300
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5-cvc5-xyz | cvc5-cvc5-xyz | cvc5-cvc5-xyz | cvc5-cvc5-xyz | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz | 0 | 280 (base +4) | 607.22 | 641.76 | 280 | 1 | 279 | 20 | 0 | 20 | 0 |
| cvc5 | 0 | 277 | 1382.37 | 1416.71 | 277 | 0 | 277 | 23 | 0 | 19 | 0 |
| SMTInterpol | 0 | 224 | 1601.87 | 1208.21 | 224 | 0 | 224 | 76 | 0 | 55 | 0 |
| z3-BooledASS ne | 0 | 1 (base -276) | 4.16 | 4.28 | 1 | 1 | 0 | 299 | 0 | 167 | 0 |
| z3-BooledASS-base n | 0 | 277 | 409.60 | 443.79 | 277 | 1 | 276 | 23 | 0 | 21 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 276 | 239.67 | 273.92 | 276 | 0 | 276 | 24 | 0 | 20 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz | 0 | 280 (base +4) | 607.22 | 641.76 | 280 | 1 | 279 | 20 | 0 | 20 | 0 |
| cvc5 | 0 | 277 | 1382.37 | 1416.71 | 277 | 0 | 277 | 23 | 0 | 19 | 0 |
| SMTInterpol | 0 | 224 | 1601.87 | 1208.21 | 224 | 0 | 224 | 76 | 0 | 55 | 0 |
| z3-BooledASS ne | 0 | 1 (base -276) | 4.16 | 4.28 | 1 | 1 | 0 | 299 | 0 | 167 | 0 |
| z3-BooledASS-base n | 0 | 277 | 409.60 | 443.79 | 277 | 1 | 276 | 23 | 0 | 21 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 276 | 239.67 | 273.92 | 276 | 0 | 276 | 24 | 0 | 20 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 1 (base +0) | 4.16 | 4.28 | 1 | 1 | 0 | 0 | 299 | 0 | 0 |
| cvc5-cvc5-xyz | 0 | 1 (base +1) | 90.29 | 90.42 | 1 | 1 | 0 | 0 | 299 | 0 | 0 |
| SMTInterpol | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 299 | 1 | 0 |
| cvc5 | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 299 | 0 | 0 |
| z3-BooledASS-base n | 0 | 1 | 4.21 | 4.35 | 1 | 1 | 0 | 0 | 299 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 299 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz | 0 | 279 (base +3) | 516.93 | 551.35 | 279 | 0 | 279 | 17 | 4 | 17 | 0 |
| cvc5 | 0 | 277 | 1382.37 | 1416.71 | 277 | 0 | 277 | 19 | 4 | 17 | 0 |
| SMTInterpol | 0 | 224 | 1601.87 | 1208.21 | 224 | 0 | 224 | 72 | 4 | 51 | 0 |
| z3-BooledASS ne | 0 | 0 (base -276) | 0.00 | 0.00 | 0 | 0 | 0 | 296 | 4 | 165 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 276 | 239.67 | 273.92 | 276 | 0 | 276 | 20 | 4 | 18 | 0 |
| z3-BooledASS-base n | 0 | 276 | 405.39 | 439.44 | 276 | 0 | 276 | 20 | 4 | 19 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 274 | 82.68 | 116.57 | 274 | 0 | 274 | 4 | 22 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 266 (base -8) | 81.05 | 113.84 | 266 | 0 | 266 | 16 | 18 | 16 | 0 |
| SMTInterpol | 0 | 194 | 403.02 | 183.66 | 194 | 0 | 194 | 1 | 105 | 0 | 0 |
| z3-BooledASS ne | 0 | 1 (base -275) | 4.16 | 4.28 | 1 | 1 | 0 | 128 | 171 | 0 | 0 |
| z3-BooledASS-base n | 0 | 276 | 94.99 | 129.00 | 276 | 1 | 275 | 0 | 24 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 274 | 86.09 | 120.09 | 274 | 0 | 274 | 4 | 22 | 0 | 0 |