The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFNRA logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 4
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 5 | 1201.094044 | 1202.502734 | 0 | 0 | 0 | 4 | 0 | 1 | 0 |
| SMTInterpol | 0 | 2 | 8794.745961 | 4808.922914 | 0 | 0 | 0 | 4 | 0 | 4 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 3 | 0.489728 | 0.7869 | 0 | 0 | 0 | 3 | 1 | 0 | 0 |