The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFLRA logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 935
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 107468 | 32486.905906 | 32621.442472 | 0 | 0 | 0 | 935 | 0 | 10 | 0 |
| SMTInterpol | 0 | 99770 | 359875.073937 | 330610.477427 | 0 | 0 | 0 | 935 | 0 | 193 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 82536 | 2756.942774 | 2853.157908 | 0 | 0 | 0 | 769 | 166 | 0 | 0 |
| SMTInterpol | 0 | 81333 | 3758.836745 | 1414.499384 | 0 | 0 | 0 | 478 | 457 | 0 | 0 |