The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFDTNIA logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 139
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 395 | 68986.052045 | 69032.855946 | 0 | 0 | 0 | 139 | 0 | 57 | 0 |
| SMTInterpol | 0 | 69 | 158927.034196 | 150268.031078 | 0 | 0 | 0 | 139 | 0 | 125 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 236 | 168.219715 | 175.977405 | 0 | 0 | 0 | 78 | 61 | 0 | 0 |
| SMTInterpol | 0 | 23 | 125.925087 | 47.260784 | 0 | 0 | 0 | 14 | 125 | 0 | 0 |