SMT-COMP 2024

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2024

UFDTLIRA (Unsat Core Track)

Competition results for the UFDTLIRA logic in the Unsat Core Track.

Results were generated on 2024-07-08

Benchmarks: 2861
Time Limit: 1200 seconds
Memory Limit: 20480 GB

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
cvc5cvc5-cvc5cvc5

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc5073057421.864853707.0935032860028601010
SMTInterpol07165612942.2282258440.8014372759027591020790

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc5073057421.864853707.0935032860028601010
SMTInterpol07165612942.2282258440.8014372759027591020790

UNSAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc5073057421.864853707.0935032860028601010
SMTInterpol07165612942.2282258440.8014372759027591020790

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc5073057421.864853707.0935032860028600100
SMTInterpol0705326518.6929642964.553254273402734112600