The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UF logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 2033
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 25960 | 1.154137110082e+06 | 1.154947600901e+06 | 0 | 0 | 0 | 2033 | 0 | 937 | 0 |
| SMTInterpol | 0 | 18002 | 5.367894714816e+06 | 1.996162428458e+06 | 0 | 0 | 0 | 2033 | 0 | 1530 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 16814 | 2496.457121 | 2593.01673 | 0 | 0 | 0 | 952 | 1081 | 0 | 0 |
| SMTInterpol | 0 | 7140 | 1791.819302 | 784.794932 | 0 | 0 | 0 | 175 | 1858 | 0 | 0 |