SMT-COMP 2024

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2024

QF_UFLIA (Model Validation Track)

Competition results for the QF_UFLIA logic in the Model Validation Track.

Results were generated on 2024-07-08

Benchmarks: 300
Time Limit: 1200 seconds
Memory Limit: 20480 GB

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
SMTInterpolSMTInterpolSMTInterpol-Yices2

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
SMTInterpol03002033.7109411139.84327430030000000
Yices202991436.0604551466.4889629929901010
cvc50297693.295923723.18136229729703030
OpenSMT02962628.8851962658.71907629629604040

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
SMTInterpol03002033.7109411139.84327430030000000
Yices202991436.0604551466.4889629929901010
cvc50297693.295923723.18136229729703030
OpenSMT02962628.8851962658.71907629629604040

SAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
SMTInterpol03002033.7109411139.84327430030000000
Yices202991436.0604551466.4889629929901010
cvc50297693.295923723.18136229729703030
OpenSMT02962628.8851962658.71907629629604040

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
Yices2029285.460627114.75739429229200800
SMTInterpol02921110.887907466.08041429229200800
cvc50291211.054849240.16729329129100900
OpenSMT0286472.701107501.34411286286001400