The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFBVLIA logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 179
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| Yices2 | - | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 207 | 33.173978 | 49.765519 | 0 | 0 | 0 | 179 | 0 | 0 | 0 |
| cvc5 | 0 | 207 | 56.521311 | 72.64592 | 0 | 0 | 0 | 179 | 0 | 0 | 0 |
| SMTInterpol | 0 | 207 | 737.79328 | 269.576109 | 0 | 0 | 0 | 179 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 207 | 33.173978 | 49.765519 | 0 | 0 | 0 | 179 | 0 | 0 | 0 |
| cvc5 | 0 | 207 | 56.521311 | 72.64592 | 0 | 0 | 0 | 179 | 0 | 0 | 0 |
| SMTInterpol | 0 | 207 | 737.79328 | 269.576109 | 0 | 0 | 0 | 179 | 0 | 0 | 0 |