SMT-COMP 2024

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2024

QF_LRA (Model Validation Track)

Competition results for the QF_LRA logic in the Model Validation Track.

Results were generated on 2024-07-08

Benchmarks: 494
Time Limit: 1200 seconds
Memory Limit: 20480 GB

Winners

winner_seqwinner_parwinner_satwinner_unsatwinner_24s
OpenSMTOpenSMTOpenSMT-Yices2

Sequential Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
OpenSMT048410216.0588410267.5991484844840100100
cvc5047517361.11961617410.6315894754750190190
Yices204724694.8134354743.2728824724720220220
SMTInterpol046729879.34087725694.5832534674670270250

Parallel Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
OpenSMT048410216.0588410267.5991484844840100100
cvc5047517361.11961617410.6315894754750190190
Yices204724694.8134354743.2728824724720220220
SMTInterpol046729879.34087725694.5832534674670270250

SAT Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
OpenSMT048410216.0588410267.5991484844840100100
cvc5047517361.11961617410.6315894754750190190
Yices204724694.8134354743.2728824724720220220
SMTInterpol046729879.34087725694.5832534674670270250

24 seconds Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
Yices20441708.740248753.090415441441005300
OpenSMT0424834.843205877.488263424424007000
cvc50380714.26744752.3256633803800011400
SMTInterpol03532072.420642887.2357173533530014100