SMT-COMP 2024

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2024

QF_LIA (Model Validation Track)

Competition results for the QF_LIA logic in the Model Validation Track.

Results were generated on 2024-07-08

Benchmarks: 4151
Time Limit: 1200 seconds
Memory Limit: 20480 GB

Winners

winner_seqwinner_parwinner_satwinner_unsatwinner_24s
cvc5cvc5cvc5-Yices2

Sequential Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc50394976029.35203376436.05325139493949020202020
OpenSMT03949219568.19047220014.93581539493949020202010
Yices20382352027.24033252421.36304538233823032803280
SMTInterpol03771138124.384662113142.20673337743774037703560

Parallel Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc50394976029.35203376436.05325139493949020202020
OpenSMT03949219568.19047220014.93581539493949020202010
Yices20382352027.24033252421.36304538233823032803280
SMTInterpol03774141865.304632116444.63202237743774037703560

SAT Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc50394976029.35203376436.05325139493949020202020
OpenSMT03949219568.19047220014.93581539493949020202010
Yices20382352027.24033252421.36304538233823032803280
SMTInterpol03774141865.304632116444.63202237743774037703560

24 seconds Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
Yices2036432558.337222922.387601364336430050800
cvc5033534051.327894386.26693335333530079800
SMTInterpol0314915528.4978177102.0068963149314900100200
OpenSMT031383766.8397774080.9136933138313801101200