SMT-COMP 2024

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2024

QF_ADT_BitVec (Model Validation Track)

Competition results for the QF_ADT_BitVec division in the Model Validation Track.

Results were generated on 2024-07-08

Benchmarks: 5247
Time Limit: 1200 seconds
Memory Limit: 20480 GB

Logics:

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
BitwuzlaBitwuzlaBitwuzla-Bitwuzla

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
Bitwuzla052155869.3015646393.84571552155215023901
cvc504946125436.818371125952.135716494649460301028511
SMTInterpol04347380109.380455324687.57359243514351089608070

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
Bitwuzla052155869.3015646393.84571552155215023901
cvc504946125436.818371125952.135716494649460301028511
SMTInterpol04351385000.735608329378.37433343514351089608070

SAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
Bitwuzla052155869.3015646393.84571552155215023901
cvc504946125436.818371125952.135716494649460301028511
SMTInterpol04351385000.735608329378.37433343514351089608070

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATSolved UNSATUnsolvedAbstainedTimeoutMemout
Bitwuzla051821265.0371551784.828162518251820184700
cvc5041645865.5633256281.9327284164416402108100
SMTInterpol0323022052.3604758699.23383732303230049196800