The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the LRA logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 5
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | SMTInterpol |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 15969 | 74.624112 | 75.135128 | 0 | 0 | 0 | 5 | 0 | 0 | 0 |
| SMTInterpol | 0 | 12722 | 1291.435653 | 1222.098657 | 0 | 0 | 0 | 5 | 0 | 1 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 12000 | 60.049043 | 20.375643 | 0 | 0 | 0 | 4 | 1 | 0 | 0 |
| cvc5 | 0 | 7443 | 19.472201 | 19.844034 | 0 | 0 | 0 | 4 | 1 | 0 | 0 |