The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the LIA logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 6
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 25393 | 17.007013 | 17.357668 | 0 | 0 | 0 | 6 | 0 | 0 | 0 |
| SMTInterpol | 0 | 25391 | 83.065262 | 27.590067 | 0 | 0 | 0 | 6 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 25393 | 17.007013 | 17.357668 | 0 | 0 | 0 | 6 | 0 | 0 | 0 |
| SMTInterpol | 0 | 25391 | 83.065262 | 27.590067 | 0 | 0 | 0 | 6 | 0 | 0 | 0 |