The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the BVFPLRA logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 9
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| Bitwuzla | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Bitwuzla | 0 | 4797 | 2494.196553 | 2496.342753 | 0 | 0 | 0 | 9 | 0 | 2 | 0 |
| cvc5 | 0 | 2964 | 7224.499453 | 7229.887894 | 0 | 0 | 0 | 9 | 0 | 6 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 2303 | 19.074896 | 19.516593 | 0 | 0 | 0 | 3 | 6 | 0 | 0 |
| Bitwuzla | 0 | 1495 | 63.44316 | 64.108741 | 0 | 0 | 0 | 6 | 3 | 0 | 0 |