The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the BV logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 18
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | Bitwuzla |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 35881 | 9392.947682 | 9398.832527 | 0 | 0 | 0 | 18 | 0 | 7 | 0 |
| Bitwuzla | 0 | 30941 | 2611.666419 | 2615.66292 | 0 | 0 | 0 | 18 | 0 | 2 | 0 |
| SMTInterpol | 0 | 22008 | 8203.939778 | 7576.801261 | 0 | 0 | 0 | 18 | 0 | 6 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Bitwuzla | 0 | 22159 | 76.095922 | 77.86734 | 0 | 0 | 0 | 14 | 4 | 0 | 0 |
| cvc5 | 0 | 19708 | 69.380506 | 70.109958 | 0 | 0 | 0 | 6 | 12 | 0 | 0 |
| SMTInterpol | 0 | 11520 | 192.45135 | 62.787209 | 0 | 0 | 0 | 9 | 9 | 0 | 0 |