The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the AUFNIRA logic in the Incremental Track.
Results were generated on 2024-07-08
Benchmarks: 165
Time Limit: 1200 seconds
Memory Limit: 20480 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 3038 | 36336.307993 | 36372.576658 | 0 | 0 | 0 | 165 | 0 | 30 | 0 |
| SMTInterpol | 0 | 1608 | 195260.599559 | 90219.844579 | 0 | 0 | 0 | 165 | 0 | 66 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 2996 | 47.664179 | 60.944129 | 0 | 0 | 0 | 133 | 32 | 0 | 0 |
| SMTInterpol | 0 | 1432 | 476.962413 | 190.60846 | 0 | 0 | 0 | 85 | 80 | 0 | 0 |