The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_Bitvec division in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 6969 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics:
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 5321 | 193709.56 | 192787.777 | 1648 | 0 | 1636 | 10 |
cvc5 | 0 | 2072 | 14523.201 | 14193.751 | 4897 | 0 | 4753 | 10 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 5321 | 193709.56 | 192787.777 | 1648 | 0 | 1636 | 10 |
cvc5 | 0 | 2072 | 14523.201 | 14193.751 | 4897 | 0 | 4753 | 10 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.