The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the BVFPLRA logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 24 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 7 | 1057.038 | 767.176 | 17 | 17 | 0 |
cvc5 | 0 | 2 | 1.726 | 1.723 | 22 | 22 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 7 | 1057.038 | 767.176 | 17 | 17 | 0 |
cvc5 | 0 | 2 | 1.726 | 1.723 | 22 | 22 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.