SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2023

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Bitvec (Proof Exhibition Track)

Competition results for the Bitvec division in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 1428
Time Limit: 1200 seconds
Memory Limit: 60 GB

Logics: This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedAbstainedTimeout Memout
cvc5-lfsc 0 1317 30477.823 30353.5381110108 0
cvc5 0 1103 1791.301 1774.9143250316 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedAbstainedTimeout Memout
cvc5-lfsc 0 131730477.82330353.5381110108 0
cvc5 0 11031791.3011774.9143250316 0

n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.