The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the AUFDTNIRA logic in the Unsat Core Track.
Page generated on 2023-07-06 16:05:43 +0000
Benchmarks: 618 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5 | cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 29672 | 50.077 | 50.029 | 1 | 0 |
cvc5 | 0 | 29409 | 49.854 | 49.606 | 2 | 0 |
Vampire | 0 | 2226 | 447.731 | 115.8 | 20 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 29672 | 50.077 | 50.029 | 1 | 0 |
cvc5 | 0 | 29409 | 49.854 | 49.606 | 2 | 0 |
Vampire | 0 | 2226 | 447.731 | 115.8 | 12 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.