The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFDTNIRA logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:25 +0000
Benchmarks: 349 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5-uc | cvc5-uc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 11722 | 1433.904 | 1434.911 | 1 | 0 |
cvc5-uc | 0 | 11506 | 8441.332 | 8443.147 | 7 | 0 |
Vampire | 0 | 1683 | 99132.381 | 58393.8 | 35 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 11722 | 1434.234 | 1434.881 | 1 | 0 |
cvc5-uc | 0 | 11506 | 8442.882 | 8442.917 | 7 | 0 |
Vampire | 0 | 1683 | 107133.741 | 52843.622 | 27 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.