The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFDTNIA logic in the Incremental Track.
Page generated on 2021-07-18 17:30:28 +0000
Benchmarks: 139 Time Limit: 1200 seconds Memory Limit: 60 GB
Parallel Performance |
---|
cvc5-inc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-inc | 0 | 528 | 18263.205 | 18262.983 | 218 | 14 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.