The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFDTLIRA logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:25 +0000
Benchmarks: 2839 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5-uc | cvc5-uc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 76554 | 141.963 | 147.204 | 0 | 0 |
cvc5-uc | 0 | 76484 | 148.685 | 149.202 | 0 | 0 |
Vampire | 0 | 17066 | 265944.439 | 107811.581 | 38 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 76554 | 141.963 | 147.204 | 0 | 0 |
cvc5-uc | 0 | 76484 | 148.685 | 149.202 | 0 | 0 |
Vampire | 0 | 17066 | 276216.299 | 101997.68 | 29 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.