The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFFPDTLIRA logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:24 +0000
Benchmarks: 112 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5-uc | cvc5-uc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 3487 | 14.29 | 11.637 | 0 | 0 |
cvc5-uc | 0 | 3481 | 12.071 | 12.02 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 3487 | 14.29 | 11.637 | 0 | 0 |
cvc5-uc | 0 | 3481 | 12.071 | 12.02 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.