The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFDTNIRA logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:24 +0000
Benchmarks: 50 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5-uc | cvc5-uc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
cvc5-uc | 0 | 1966 | 5.998 | 5.996 | 0 | 0 |
2020-CVC4-ucn | 0 | 1950 | 5.125 | 5.122 | 0 | 0 |
Vampire | 0 | 99 | 19226.316 | 7062.604 | 2 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
cvc5-uc | 0 | 1966 | 5.998 | 5.996 | 0 | 0 |
2020-CVC4-ucn | 0 | 1950 | 5.125 | 5.122 | 0 | 0 |
Vampire | 0 | 99 | 19424.096 | 5354.631 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.