The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the AUFDTLIRA logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:24 +0000
Benchmarks: 4950 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5-uc | cvc5-uc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 193188 | 10147.058 | 10164.77 | 8 | 0 |
cvc5-uc | 0 | 192840 | 13911.687 | 13912.711 | 10 | 0 |
Vampire | 0 | 50100 | 1135543.164 | 808152.221 | 566 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 193188 | 10150.218 | 10164.29 | 8 | 0 |
cvc5-uc | 0 | 192840 | 13913.527 | 13912.151 | 10 | 0 |
Vampire | 0 | 50467 | 1264504.104 | 667248.392 | 369 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.