The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFIDL division as of Fri Oct 30 12:49:29 GMT
Competition benchmarks = 68
Competition industrial benchmarks = 68
| Sequential Performance | Sequential Performance (industrial) | Parallel Performance | Parallel Performance (industrial) |
|---|---|---|---|
| CVC4 | CVC4 | CVC4 | CVC4 |
| Solver | Errors | Corrects | CPU |
|---|---|---|---|
| CVC3 | 0 | 0 | 0.58 |
| CVC4 | 0 | 64 | 768.33 |
| CVC4 (exp) | 0 | 64 | 768.54 |
| z3n | 0 | 66 | 4803.20 |
| veriT | 0 | 57 | 14141.50 |
| Solver | Errors | Corrects | CPU |
|---|---|---|---|
| CVC3 | 0 | 0 | 0.58 |
| CVC4 | 0 | 64 | 768.33 |
| CVC4 (exp) | 0 | 64 | 768.54 |
| z3n | 0 | 66 | 4803.20 |
| veriT | 0 | 57 | 14141.50 |
| Solver | Errors | Corrects | CPU | WALL |
|---|---|---|---|---|
| CVC3 | 0 | 0 | 0.58 | 0.70 |
| CVC4 | 0 | 64 | 768.33 | 768.34 |
| CVC4 (exp) | 0 | 64 | 768.54 | 768.86 |
| z3n | 0 | 66 | 4805.03 | 4803.23 |
| veriT | 0 | 57 | 14145.75 | 14140.51 |
| Solver | Errors | Corrects | CPU | WALL |
|---|---|---|---|---|
| CVC3 | 0 | 0 | 0.58 | 0.70 |
| CVC4 | 0 | 64 | 768.33 | 768.34 |
| CVC4 (exp) | 0 | 64 | 768.54 | 768.86 |
| z3n | 0 | 66 | 4805.03 | 4803.23 |
| veriT | 0 | 57 | 14145.75 | 14140.51 |
| Solver | Not Solved | Remaining |
|---|---|---|
| CVC3 | 68 | 0 |
| CVC4 | 4 | 0 |
| CVC4 (exp) | 4 | 0 |
| z3n | 2 | 0 |
| veriT | 11 | 0 |
n. Non-competitive.