The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFIDL division as of Fri Oct 30 12:49:29 GMT
Competition benchmarks = 441
Competition industrial benchmarks = 422
Sequential Performance | Sequential Performance (industrial) | Parallel Performance | Parallel Performance (industrial) |
---|---|---|---|
Yices | Yices | Yices | Yices |
Solver | Errors | Corrects | CPU |
---|---|---|---|
CVC4 | 0 | 412 | 92036.91 |
CVC4 (exp) | 0 | 412 | 91937.68 |
SMTInterpol | 0 | 423 | 56364.33 |
Yices | 0 | 439 | 5510.08 |
z3n | 0 | 439 | 5812.97 |
veriT | 0 | 414 | 69573.38 |
Solver | Errors | Corrects | CPU |
---|---|---|---|
CVC4 | 0 | 404 | 62838.62 |
CVC4 (exp) | 0 | 404 | 62766.06 |
SMTInterpol | 0 | 404 | 56204.27 |
Yices | 0 | 420 | 5496.56 |
z3n | 0 | 420 | 5807.85 |
veriT | 0 | 401 | 64879.02 |
Solver | Errors | Corrects | CPU | WALL |
---|---|---|---|---|
CVC4 | 0 | 412 | 92063.10 | 92009.12 |
CVC4 (exp) | 0 | 412 | 91964.66 | 91893.91 |
SMTInterpol | 0 | 423 | 57104.25 | 54811.36 |
Yices | 0 | 439 | 5511.62 | 5510.70 |
z3n | 0 | 439 | 5815.03 | 5812.69 |
veriT | 0 | 414 | 69592.04 | 69567.04 |
Solver | Errors | Corrects | CPU | WALL |
---|---|---|---|---|
CVC4 | 0 | 404 | 62854.03 | 62811.81 |
CVC4 (exp) | 0 | 404 | 62781.46 | 62723.20 |
SMTInterpol | 0 | 404 | 56944.19 | 54724.99 |
Yices | 0 | 420 | 5498.10 | 5497.17 |
z3n | 0 | 420 | 5809.91 | 5807.57 |
veriT | 0 | 401 | 64897.68 | 64874.53 |
Solver | Not Solved | Remaining |
---|---|---|
CVC4 | 29 | 0 |
CVC4 (exp) | 29 | 0 |
SMTInterpol | 18 | 0 |
Yices | 2 | 0 |
z3n | 2 | 0 |
veriT | 27 | 0 |
n. Non-competitive.