The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_LIRA division as of Fri Oct 30 12:49:29 GMT
Competition benchmarks = 6
Competition industrial benchmarks = 6
Sequential Performance | Sequential Performance (industrial) | Parallel Performance | Parallel Performance (industrial) |
---|---|---|---|
Yices | Yices | Yices | Yices |
Solver | Errors | Corrects | CPU |
---|---|---|---|
CVC4 | 0 | 6 | 847.21 |
CVC4 (exp) | 0 | 6 | 866.44 |
SMT-RAT | 0 | 5 | 2796.40 |
SMTInterpol | 0 | 3 | 7214.75 |
Yices | 0 | 6 | 259.65 |
z3n | 0 | 5 | 72.71 |
Solver | Errors | Corrects | CPU |
---|---|---|---|
CVC4 | 0 | 6 | 847.21 |
CVC4 (exp) | 0 | 6 | 866.44 |
SMT-RAT | 0 | 5 | 2796.40 |
SMTInterpol | 0 | 3 | 7214.75 |
Yices | 0 | 6 | 259.65 |
z3n | 0 | 5 | 72.71 |
Solver | Errors | Corrects | CPU | WALL |
---|---|---|---|---|
CVC4 | 0 | 6 | 847.21 | 847.13 |
CVC4 (exp) | 0 | 6 | 866.44 | 866.30 |
SMT-RAT | 0 | 5 | 2797.63 | 2796.39 |
SMTInterpol | 0 | 3 | 7297.05 | 7206.50 |
Yices | 0 | 6 | 259.65 | 259.56 |
z3n | 0 | 5 | 72.71 | 72.68 |
Solver | Errors | Corrects | CPU | WALL |
---|---|---|---|---|
CVC4 | 0 | 6 | 847.21 | 847.13 |
CVC4 (exp) | 0 | 6 | 866.44 | 866.30 |
SMT-RAT | 0 | 5 | 2797.63 | 2796.39 |
SMTInterpol | 0 | 3 | 7297.05 | 7206.50 |
Yices | 0 | 6 | 259.65 | 259.56 |
z3n | 0 | 5 | 72.71 | 72.68 |
Solver | Not Solved | Remaining |
---|---|---|
CVC4 | 0 | 0 |
CVC4 (exp) | 0 | 0 |
SMT-RAT | 1 | 0 |
SMTInterpol | 3 | 0 |
Yices | 0 | 0 |
z3n | 1 | 0 |
n. Non-competitive.