SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions

SMT-COMP 2015

Rules
Benchmarks
Tools
Specs
Participants
Results
Slides
Report

QF_LIA (Main Track)

Competition results for the QF_LIA division as of Fri Oct 30 12:49:29 GMT

Competition benchmarks = 5839
Competition industrial benchmarks = 4102

The winners for this division are:

Sequential Performance

Sequential Performance Sequential Performance (industrial) Parallel Performance Parallel Performance (industrial)
CVC4 (exp) Yices CVC4 (exp) Yices

Division COMPLETE

Sequential Performance

SolverErrors Corrects CPU
CVC4 0 5678 546345.04
CVC4 (exp) 0 5678 546052.01
SMT-RAT 0 2196 8935239.72
SMTInterpol 0 5583 802877.37
Yices 0 5638 577864.36
MathSatn 0 5710 412224.72
z3n 0 5592 742614.82
veriT 0 2158 6630467.91

Sequential Performance (industrial)

SolverErrors Corrects CPU
CVC4 0 3966 472510.82
CVC4 (exp) 0 3966 472218.84
SMT-RAT 0 1065 7446899.21
SMTInterpol 0 3865 732526.46
Yices 0 3990 313169.18
MathSatn 0 4015 289785.01
z3n 0 4035 266839.13
veriT 0 1322 6601769.72

Parallel Performance

SolverErrors Corrects CPU WALL
CVC4 0 5678 546495.10 546113.47
CVC4 (exp) 0 5678 546205.02 545919.35
SMT-RAT 0 2196 8938446.33 8935236.01
SMTInterpol 0 5589 1064296.52 753336.28
Yices 0 5638 578043.43 577838.32
MathSatn 0 5710 412336.47 412095.28
z3n 0 5592 742856.58 742379.50
veriT 0 2158 6632991.67 6630396.75

Parallel Performance (industrial)

SolverErrors Corrects CPU WALL
CVC4 0 3966 472640.61 472282.56
CVC4 (exp) 0 3966 472350.96 472092.81
SMT-RAT 0 1065 7449589.70 7446905.49
SMTInterpol 0 3871 978350.47 687552.04
Yices 0 3990 313266.13 313157.37
MathSatn 0 4015 289857.28 289728.44
z3n 0 4035 266900.93 266619.58
veriT 0 1322 6604285.68 6601699.68

Other Information

Solver Not Solved Remaining
CVC4 161 0
CVC4 (exp) 161 0
SMT-RAT 3643 0
SMTInterpol 250 0
Yices 201 0
MathSatn 129 0
z3n 247 0
veriT 3681 0

n. Non-competitive.